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Integrated Device Technology, Inc.
HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
DESCRIPTION:
ADVANCED IDT707288S/L
FEATURES:
* 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks - 1 Megabit of memory on chip * Fast asynchronous address-to-data access time: 20ns * User-controlled input pins included for bank selects * Independent port controls with asynchronous address & data busses * Four 16-bit mailboxes available to each port for interprocessor communications; interrupt option * Interrupt flags with programmable masking * Dual Chip Enables allow for depth expansion without external logic * UB and LB are available for bus matching to x8 or x16 busses; also support very fast banking * TTL-compatible, single 5V (10%) power supply * Available in a 100-pin Thin Quad Plastic Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA)
The IDT707288 is a high-speed 64K x 16 (1M bit) BankSwitchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate controls, addresses, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow inter-processor communications. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288 offers a maximum address-to-data access time as fast as 20ns, while typically operating on only 900mW of power, and is available in a 100-pin Thin Quad Plastic Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
R/
FUNCTIONAL BLOCK DIAGRAM
R/
L 0L
MUX
R 0R
CE1L
L L L
CONTROL LOGIC
16Kx16 MEMORY ARRAY (BANK 0) MUX
CONTROL LOGIC
CE1R
R R R
I/O8L-15L I/O0L-7L
I/O CONTROL
MUX 16Kx16 MEMORY ARRAY (BANK 1) MUX
I/O CONTROL
I/O8R-15R I/O0R-7R
A13L A0L(1)
ADDRESS DECODE
ADDRESS DECODE
A13R A0R(1)
BA1L BA0L
BANK DECODE MUX 16Kx16 MEMORY ARRAY (BANK 3) MUX
BANK DECODE
BA1R BA0R
BKSEL3(2) BKSEL0(2)
BANK SELECT A5L(1) A0L(1)
L/ L L L L L L
MAILBOX INTERRUPT LOGIC
A5R(1) A0R(1)
R/ R R
R/
R/
R
R R R
3592 drw 01
NOTES: 1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-3592/-
6.29
1
IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
FUNCTIONALITY:
The IDT707288 is a high-speed asynchronous 64K x 16 Bank-Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array. There are four user-controlled Bank Select input pins , and each of these pins is associated with a specific bank within the memory array. Access to a specific bank is gained by placing the associated Bank Select pin in the appropriate state: VIH assigns the bank to the left port, and VIL assigns the bank to the right port (See Truth Table I). Once a bank is assigned to a particular port, the port has full access to read and write within that bank. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The IDT707288 provides mailboxes to allow inter-processor communications. Each port has four 16-bit mailbox registers available to which it can write and read and which the opposite port can read only. These mailboxes are external to the common SRAM array, and are accessed by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an associated interrupt: a port can generate an interrupt to the opposite port by writing to the upper byte of any one of its four 16-bit mailboxes. The interrupted port can clear the interrupt by reading the upper byte. This read will not alter the contents of the mailbox. If desired, any source of interrupt can be independently masked via software. Two registers are provided to permit interpretation of interrupts: the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to. The information
in this register provides post-mask signals: Interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. Truth Table II gives a detailed explanation of the use of these registers.
PIN NAMES
A0 - A13 (1,6) BA0 - BA1
MBSEL (1)
(1)
Address Inputs Bank Address Inputs Mailbox Access Control Gate Bank Select Inputs Read/Write Enable Output Enable Chip Enables I/O Byte Enables Bidirectional Data Input/Output Interrupt Flag (Output)(3) +5V Power Ground
BKSEL R/W (1)
OE
(1)
(2)
CE0,
CE1 (1)
UB, LB (1)
I/O0 - I/O15 (1)
INT (1)
VCC GND (5)
(4)
3592 tbl 01 NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details. 3. Generated upon mailbox access. 4. All Vcc pins must be connected to power supply. 5. All GND pins must be connected to ground supply. 6. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as bank address or memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs.
PIN CONFIGURATIONS (1,2)
GND GND
I NTR I NTL
INDEX
A6L A7L A8L A9L A10L A11L A13L NC BKSEL0
LBL UBL CE0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 1 2 3
CE1L
MBS ELL
Vcc R/WL
OEL
GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
76 75 74 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 IDT707288 11 65 PN100-1 12 64 13 63 100-PIN TQFP 14 62 15 61 TOP VIEW(3) 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A5L A4L A3L A2L A1L A0L BA1L BA0L A12L NC BKSEL1
BKSEL2 A12R BA0R BA1R A0R A1R A2R A3R A4R A5R
A6R A7R A8R A9R A10R A11R A13R NC BKSEL3
LBR UBR CE0R
CE1R
MBS ELR
GND R/WR
O ER
GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
3592 drw 02
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.29 2
I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC
IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CON'T.) (1,2)
81 80 77 74 72
UBR
69
MB SEL R
68
65
63
60
57
54
12
A7R
84
A8R
83
A11R
78
BK SEL3
76
GND GND
67 64
NC
61
I/O13R I/O10R
59 56
NC
53
73
LBR
70
11
A4R
87
A5R
86
A10R
82
A13R
79
CE1R R/WR
71
CE0R
GND I/O14R I/O12R I/O9R
62 58 55 51
NC
50
75
66
OER
10
A1R
90
A2R
88
A6R
85
A9R
NC
I/O15R I/O11R
NC
52
I/O8R
49
I/O7R
47
09
BA0R
92
A0R
91
A3R
89
NC
48
Vcc
46
I/O5R
45
08
BK SEL2
95
A12R
94
BA1R
93
INTR
I/O6R
44
I/O4R
43
I/O3R
42
07
GND
96
GND
97
IDT707288 G108-1
I/O2R
39
I/O1R
40
I/O0R
41
98
06
INTL
BK SEL1
100
NC
102
I/O1L
108-Pin PGA Top View
(3)
I/O0L
37
GND
38
99
35
05
A12L
101
BA0L
103
A0L
106
I/O4L
31
I/O2L
34
GND
36
04
BA1L
104
A1L
105 1
A4L
4 8 12 17 21 25
Vcc
28
I/O5L
32
I/O3L
33
03
A2L
107 2
A3L
5
A7L
7
A10L
BK SEL0
10
UBL
CE1L
13
MB SELL
GND
16
OEL
I/O14L I/O10L
19 22
NC
24
I/O7L
29
I/O6L
30
02
A5L
108
A8L
3 6
A11L
9
NC
GND I/O13L
18 20
I/O11L
23 26
NC
I/O8L
27
11
LBL CE0L
14
15
01
A6L A
A9L B
A13L C
Vcc F
R/WL G
NC H
I/O15L J
I/O12L K
I/O9L L
NC M
3592 drw 03
D
E
I NDEX
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking.
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IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
ASSIGNING THE BANKS VIA THE EXTERNAL BANK SELECTS There are four bank select pins available on the IDT707288, and each of these pins is associated with a specific bank within the memory array. The pins are user-controlled inputs: access to a specific bank is assigned to a particular port by setting the input to the appropriate level. The process of assigning the banks is detailed in Truth Table I. Once a bank is assigned to a port, the owning port has full access to read and write within that bank. The opposite port is unable to access that bank until the user reassigns the port. Access by
a port to a bank which it does not control will have no effect if written, and if read unknown values on D0-D15 will be returned. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The bank select pin inputs must be set at either VIH or VIL - these inputs are not tri-statable. When changing the bank select inputs (changing the bank assignments), the device must be write-disabled (CE and/or R/W set to VIH).
TRUTH TABLE I - MEMORY BANK ASSIGNMENT (CE AND/OR R/W = VIH)(2,3) CE W
BANK AND BKSEL0 H X X X L X X X BKSEL1 X H X X X L X X BKSEL2 X X H X X X L X BKSEL3 X X X H X X X L DIRECTION(1) BANK 0 LEFT BANK 1 LEFT BANK 2 LEFT BANK 3 LEFT BANK 0 RIGHT BANK 1 RIGHT BANK 2 RIGHT BANK 3 RIGHT
NOTES: 3592 tbl 02 1. Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second 16Kx16 memory spaces, Bank 2 to the third 16Kx16 memory spaces, and Bank 3 to the fourth 16Kx16 memory spaces. 'LEFT' indicates the bank is assigned to the left port; 'RIGHT' indicates the bank is assigned to the right port. 2. The bank select pin inputs must be set at either VIH or VIL - these inputs are not tri-statable. When changing the bank select inputs (changing the bank assignments), the device must be write-disabled (CE and/or R/W set to VIH). 3. 'H' = VIH, 'L' = VIL, 'X' = Don't Care.
MAILBOX INTERRUPTS AND INTERRUPT CONTROL REGISTERS If the user chooses to use the mailbox interrupt function, four mailbox locations are assigned to each port. These mailbox locations are external to the memory array. The mailboxes are accessed by taking MBSEL Low while holding CE High. The mailboxes are 16 bits wide: the message is userdefined since these are addressable SRAM locations. An interrupt is generated to the opposite port upon writing to the upper byte of any mailbox location. A port can read the message it has just written in order to verify it: this read will not alter the status of the interrupt sent to the opposite port. The interrupted port can clear the interrupt by reading the upper byte of the applicable mailbox. This read will not alter the contents of the mailbox. The use of mailboxes to generate interrupts to the opposite port and the reading of mailboxes to clear interrupts is detailed in Truth Table II. If desired, any of the mailbox interrupts can be independently masked via software. Masking of the interrupt sources
is done in the Mask Register. The masks are individual and independent: a port can mask any combination of interrupt sources with no effect on the other sources. Each port can modify only its own Mask Register. The use of this register is detailed in Truth Table II. Two registers are provided to permit interpretation of interrupts: these are the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - a specific semaphore granted to that port or a specific mailbox written to by the opposite port. The information in this register provides post-mask signals: interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. The use of the Interrupt Cause Register and the Interrupt Status Register is detailed in Truth Table II.
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IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE II - MAILBOX INTERRUPTS (CE = VIH)(8,9) CE
MB SEL
L L L L L L R/W X X (1) (1) (1) (1) H H H H L L L (3) X X
UB LB
X X (1) (1) (1) (1) (2) (2) (2) (2) (3) X X X X (1) (1) (1) (1) (2) (2) (2) (2) (3) X X
A5 L
A4 A3 L L
A2 L
A1 A0 L L
D0
D1
D2 D3
D4
D5
D6 D7
D8
D9 D10 D11 D12 D13 D14 D15
DESCRIPTION RESERVED (7) RESERVED (7)
RESERVED (7) RESERVED (7)
H H H H H H H H H
L L L L L L L L L
L L L L L L L L H
L L L L H H H H L
L L H H L L H H L
L H L H L H L H L
X X X X X X X X (4)
X X X X X X X X (4)
X X X X X X X X (4)
X X X X X X X X (4)
X X X X X X X X (5)
X X X X X X X X (5)
X X X X X X X X (5)
X X X X X X X X (5)
X X X X X X X X (6)
X X X X X X X X (6)
X X X X X X X X (6)
X X X X X X X X (6)
X X X X X X X X X
X X X X X X X X X
X X X X X X X X X
X X X X X X X X X
MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX INTERRUPT CONTROLS RESERVED (7) RESERVED (7)
RESERVED (7) H H H H H H RESERVED (7)
3592 tbl 03 NOTES: 1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in either 8-bit or 16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be individually masked if desired, and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port can read its own mailboxes to verify the data written, without affecting the interrupt which is sent to the opposite port. 2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a particular mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the actual clearing of the interrupt is triggered by the transition of MBSEL from VIH to VIL. 3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The controls for R/W, UB, and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are "Don't Care". 4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 = Mailbox 0, D1 = Mailbox 1, D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this register must be written at the same time. This register can be read at any time to verify the mask settings. The masks are individual and independent: any single interrupt source can be masked with no effect on the other sources. Each port can modify only its own mask settings. 5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific bit (D4 = Mailbox 0, D5 = Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt source has been masked, the associated bit in this register will not update. 6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of whether they have been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for this table). This register provides pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this register will update. 7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned. 8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these registers. 9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.
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IDT707288S/L 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range
Blank
Commercial (0C to +70C)
PF G
100-pin TQFP (PN100-1) 108-pin PGA (G108-1)
20 25
Commercial Only Commercial Only
Speed in nanoseconds
S L
Standard Power Low Power
707288 1Mbit (4 x 16K x 16) Bank-Switchable Dual-Ported SRAM with External Bank Selects
3592 drw 19
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